source: freewrt/package/robocfg/etc53xx.h@ 428f140

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Last change on this file since 428f140 was 475ad56, checked in by Waldemar Brodkorb <wbx@…>, 20 years ago

add OpenWrt trunk revision 3830.

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1/*
2 * Broadcom Home Gateway Reference Design
3 * BCM53xx Register definitions
4 *
5 * Copyright 2004, Broadcom Corporation
6 * All Rights Reserved.
7 *
8 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
11 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
12 * $Id: etc53xx.h 889 2005-05-14 13:15:46Z nbd $
13 */
14
15#ifndef __BCM535M_H_
16#define __BCM535M_H_
17
18/* ROBO embedded device type */
19#define ROBO_DEV_5380 1
20#define ROBO_DEV_5365 2
21#define ROBO_DEV_5350 3
22
23/* BCM5325m GLOBAL PAGE REGISTER MAP */
24#ifndef _CFE_
25#pragma pack(1)
26#endif
27
28/* BCM5325m Serial Management Port (SMP) Page offsets */
29#define ROBO_CTRL_PAGE 0x00 /* Control registers */
30#define ROBO_STAT_PAGE 0x01 /* Status register */
31#define ROBO_MGMT_PAGE 0x02 /* Management Mode registers */
32#define ROBO_MIB_AC_PAGE 0x03 /* MIB Autocast registers */
33#define ROBO_ARLCTRL_PAGE 0x04 /* ARL Control Registers */
34#define ROBO_ARLIO_PAGE 0x05 /* ARL Access Registers */
35#define ROBO_FRAMEBUF_PAGE 0x06 /* Management frame access registers */
36#define ROBO_MEM_ACCESS_PAGE 0x08 /* Memory access registers */
37
38/* PHY Registers */
39#define ROBO_PORT0_MII_PAGE 0x10 /* Port 0 MII Registers */
40#define ROBO_PORT1_MII_PAGE 0x11 /* Port 1 MII Registers */
41#define ROBO_PORT2_MII_PAGE 0x12 /* Port 2 MII Registers */
42#define ROBO_PORT3_MII_PAGE 0x13 /* Port 3 MII Registers */
43#define ROBO_PORT4_MII_PAGE 0x14 /* Port 4 MII Registers */
44/* (start) registers only for BCM5380 */
45#define ROBO_PORT5_MII_PAGE 0x15 /* Port 5 MII Registers */
46#define ROBO_PORT6_MII_PAGE 0x16 /* Port 6 MII Registers */
47#define ROBO_PORT7_MII_PAGE 0x17 /* Port 7 MII Registers */
48/* (end) registers only for BCM5380 */
49#define ROBO_IM_PORT_PAGE 0x18 /* Inverse MII Port (to EMAC) */
50#define ROBO_ALL_PORT_PAGE 0x19 /* All ports MII Registers (broadcast)*/
51
52/* MAC Statistics registers */
53#define ROBO_PORT0_MIB_PAGE 0x20 /* Port 0 10/100 MIB Statistics */
54#define ROBO_PORT1_MIB_PAGE 0x21 /* Port 1 10/100 MIB Statistics */
55#define ROBO_PORT2_MIB_PAGE 0x22 /* Port 2 10/100 MIB Statistics */
56#define ROBO_PORT3_MIB_PAGE 0x23 /* Port 3 10/100 MIB Statistics */
57#define ROBO_PORT4_MIB_PAGE 0x24 /* Port 4 10/100 MIB Statistics */
58/* (start) registers only for BCM5380 */
59#define ROBO_PORT5_MIB_PAGE 0x25 /* Port 5 10/100 MIB Statistics */
60#define ROBO_PORT6_MIB_PAGE 0x26 /* Port 6 10/100 MIB Statistics */
61#define ROBO_PORT7_MIB_PAGE 0x27 /* Port 7 10/100 MIB Statistics */
62/* (end) registers only for BCM5380 */
63#define ROBO_IM_PORT_MIB_PAGE 0x28 /* Inverse MII Port MIB Statistics */
64
65/* Quality of Service (QoS) Registers */
66#define ROBO_QOS_PAGE 0x30 /* QoS Registers */
67
68/* VLAN Registers */
69#define ROBO_VLAN_PAGE 0x34 /* VLAN Registers */
70
71/* Note SPI Data/IO Registers not used */
72#define ROBO_SPI_DATA_IO_0_PAGE 0xf0 /* SPI Data I/O 0 */
73#define ROBO_SPI_DATA_IO_1_PAGE 0xf1 /* SPI Data I/O 1 */
74#define ROBO_SPI_DATA_IO_2_PAGE 0xf2 /* SPI Data I/O 2 */
75#define ROBO_SPI_DATA_IO_3_PAGE 0xf3 /* SPI Data I/O 3 */
76#define ROBO_SPI_DATA_IO_4_PAGE 0xf4 /* SPI Data I/O 4 */
77#define ROBO_SPI_DATA_IO_5_PAGE 0xf5 /* SPI Data I/O 5 */
78#define ROBO_SPI_DATA_IO_6_PAGE 0xf6 /* SPI Data I/O 6 */
79#define ROBO_SPI_DATA_IO_7_PAGE 0xf7 /* SPI Data I/O 7 */
80
81#define ROBO_SPI_STATUS_PAGE 0xfe /* SPI Status Registers */
82#define ROBO_PAGE_PAGE 0xff /* Page Registers */
83
84
85/* BCM5325m CONTROL PAGE (0x00) REGISTER MAP : 8bit (byte) registers */
86typedef struct _ROBO_PORT_CTRL_STRUC
87{
88 unsigned char rx_disable:1; /* rx disable */
89 unsigned char tx_disable:1; /* tx disable */
90 unsigned char rsvd:3; /* reserved */
91 unsigned char stp_state:3; /* spanning tree state */
92} ROBO_PORT_CTRL_STRUC;
93
94#define ROBO_PORT0_CTRL 0x00 /* 10/100 Port 0 Control */
95#define ROBO_PORT1_CTRL 0x01 /* 10/100 Port 1 Control */
96#define ROBO_PORT2_CTRL 0x02 /* 10/100 Port 2 Control */
97#define ROBO_PORT3_CTRL 0x03 /* 10/100 Port 3 Control */
98#define ROBO_PORT4_CTRL 0x04 /* 10/100 Port 4 Control */
99/* (start) registers only for BCM5380 */
100#define ROBO_PORT5_CTRL 0x05 /* 10/100 Port 5 Control */
101#define ROBO_PORT6_CTRL 0x06 /* 10/100 Port 6 Control */
102#define ROBO_PORT7_CTRL 0x07 /* 10/100 Port 7 Control */
103/* (end) registers only for BCM5380 */
104#define ROBO_IM_PORT_CTRL 0x08 /* 10/100 Port 8 Control */
105#define ROBO_SMP_CTRL 0x0a /* SMP Control register */
106#define ROBO_SWITCH_MODE 0x0b /* Switch Mode Control */
107#define ROBO_PORT_OVERRIDE_CTRL 0x0e /* Port state override */
108#define ROBO_PORT_OVERRIDE_RVMII (1<<4) /* Bit 4 enables RvMII */
109#define ROBO_PD_MODE_CTRL 0x0f /* Power-down mode control */
110#define ROBO_IP_MULTICAST_CTRL 0x21 /* IP Multicast control */
111
112/* BCM5325m STATUS PAGE (0x01) REGISTER MAP : 16bit/48bit registers */
113#define ROBO_HALF_DUPLEX 0
114#define ROBO_FULL_DUPLEX 1
115
116#define ROBO_LINK_STAT_SUMMARY 0x00 /* Link Status Summary: 16bit */
117#define ROBO_LINK_STAT_CHANGE 0x02 /* Link Status Change: 16bit */
118#define ROBO_SPEED_STAT_SUMMARY 0x04 /* Port Speed Summary: 16bit*/
119#define ROBO_DUPLEX_STAT_SUMMARY 0x06 /* Duplex Status Summary: 16bit */
120#define ROBO_PAUSE_STAT_SUMMARY 0x08 /* PAUSE Status Summary: 16bit */
121#define ROBO_SOURCE_ADDR_CHANGE 0x0C /* Source Address Change: 16bit */
122#define ROBO_LSA_PORT0 0x10 /* Last Source Addr, Port 0: 48bits*/
123#define ROBO_LSA_PORT1 0x16 /* Last Source Addr, Port 1: 48bits*/
124#define ROBO_LSA_PORT2 0x1c /* Last Source Addr, Port 2: 48bits*/
125#define ROBO_LSA_PORT3 0x22 /* Last Source Addr, Port 3: 48bits*/
126#define ROBO_LSA_PORT4 0x28 /* Last Source Addr, Port 4: 48bits*/
127#define ROBO_LSA_IM_PORT 0x40 /* Last Source Addr, IM Port: 48bits*/
128
129/* BCM5325m MANAGEMENT MODE REGISTERS (0x02) REGISTER MAP: 8/48 bit regs*/
130typedef struct _ROBO_GLOBAL_CONFIG_STRUC
131{
132 unsigned char resetMIB:1; /* reset MIB counters */
133 unsigned char rxBPDU:1; /* receive BDPU enable */
134 unsigned char rsvd1:2; /* reserved */
135 unsigned char MIBacHdrCtrl:1; /* MIB autocast header control */
136 unsigned char MIBac:1; /* MIB autocast enable */
137 unsigned char frameMgmtPort:2; /* frame management port */
138} ROBO_GLOBAL_CONFIG_STRUC;
139#define ROBO_GLOBAL_CONFIG 0x00 /* Global Management Config: 8bit*/
140#define ROBO_MGMT_PORT_ID 0x02 /* Management Port ID: 8bit*/
141#define ROBO_RMON_MIB_STEER 0x04 /* RMON Mib Steering: 16bit */
142#define ROBO_MIB_MODE_SELECT 0x04 /* MIB Mode select: 16bit (BCM5350) */
143#define ROBO_AGE_TIMER_CTRL 0x06 /* Age time control: 32bit */
144#define ROBO_MIRROR_CAP_CTRL 0x10 /* Mirror Capture : 16bit */
145#define ROBO_MIRROR_ING_CTRL 0x12 /* Mirror Ingress Control: 16bit */
146#define ROBO_MIRROR_ING_DIV_CTRL 0x14 /* Mirror Ingress Divider: 16bit */
147#define ROBO_MIRROR_ING_MAC_ADDR 0x16 /* Ingress Mirror MAC Addr: 48bit*/
148#define ROBO_MIRROR_EGR_CTRL 0x1c /* Mirror Egress Control: 16bit */
149#define ROBO_MIRROR_EGR_DIV_CTRL 0x1e /* Mirror Egress Divider: 16bit */
150#define ROBO_MIRROR_EGR_MAC_ADDR 0x20 /* Egress Mirror MAC Addr: 48bit*/
151
152/* BCM5325m MIB AUTOCAST REGISTERS (0x03) REGISTER MAP: 8/16/48 bit regs */
153#define ROBO_MIB_AC_PORT 0x00 /* MIB Autocast Port: 16bit */
154#define ROBO_MIB_AC_HDR_PTR 0x02 /* MIB Autocast Header pointer:16bit*/
155#define ROBO_MIB_AC_HDR_LEN 0x04 /* MIB Autocast Header Len: 16bit */
156#define ROBO_MIB_AC_DA 0x06 /* MIB Autocast DA: 48bit */
157#define ROBO_MIB_AC_SA 0x0c /* MIB Autocast SA: 48bit */
158#define ROBO_MIB_AC_TYPE 0x12 /* MIB Autocast Type: 16bit */
159#define ROBO_MIB_AC_RATE 0x14 /* MIB Autocast Rate: 8bit */
160#define ROBO_GET_AC_RATE(secs) ((secs)*10)
161#define ROBO_AC_RATE_MAX 0xff
162#define ROBO_AC_RATE_DEFAULT 0x64 /* 10 secs */
163typedef struct _ROBO_MIB_AC_STRUCT
164{
165 unsigned char opcode:4; /* Tx MIB Autocast opcode */
166 unsigned char portno:4; /* zero-based port no. */
167 unsigned char portstate:8; /* port state */
168 unsigned long long TxOctets;
169 unsigned int TxDropPkts;
170 unsigned int rsvd;
171 unsigned int TxBroadcastPkts;
172 unsigned int TxMulticastPkts;
173 unsigned int TxUnicastPkts;
174 unsigned int TxCollisions;
175 unsigned int TxSingleCollision;
176 unsigned int TxMultiCollision;
177 unsigned int TxDeferredTransmit;
178 unsigned int TxLateCollision;
179 unsigned int TxExcessiveCollision;
180 unsigned int TxFrameInDiscards;
181 unsigned int TxPausePkts;
182 unsigned int rsvd1[2];
183 unsigned long long RxOctets;
184 unsigned int RxUndersizePkts;
185 unsigned int RxPausePkts;
186 unsigned int RxPkts64Octets;
187 unsigned int RxPkts64to127Octets;
188 unsigned int RxPkts128to255Octets;
189 unsigned int RxPkts256to511Octets;
190 unsigned int RxPkts512to1023Octets;
191 unsigned int RxPkts1024to1522Octets;
192 unsigned int RxOversizePkts;
193 unsigned int RxJabbers;
194 unsigned int RxAlignmentErrors;
195 unsigned int RxFCSErrors;
196 unsigned long long RxGoodOctets;
197 unsigned int RxDropPkts;
198 unsigned int RxUnicastPkts;
199 unsigned int RxMulticastPkts;
200 unsigned int RxBroadcastPkts;
201 unsigned int RxSAChanges;
202 unsigned int RxFragments;
203 unsigned int RxExcessSizeDisc;
204 unsigned int RxSymbolError;
205} ROBO_MIB_AC_STRUCT;
206
207/* BCM5325m ARL CONTROL REGISTERS (0x04) REGISTER MAP: 8/16/48/64 bit regs */
208#define ROBO_ARL_CONFIG 0x00 /* ARL Global Configuration: 8bit*/
209#define ROBO_BPDU_MC_ADDR_REG 0x04 /* BPDU Multicast Address Reg:64bit*/
210#define ROBO_MULTIPORT_ADDR_1 0x10 /* Multiport Address 1: 48 bits*/
211#define ROBO_MULTIPORT_VECTOR_1 0x16 /* Multiport Vector 1: 16 bits */
212#define ROBO_MULTIPORT_ADDR_2 0x20 /* Multiport Address 2: 48 bits*/
213#define ROBO_MULTIPORT_VECTOR_2 0x26 /* Multiport Vector 2: 16 bits */
214#define ROBO_SECURE_SRC_PORT_MASK 0x30 /* Secure Source Port Mask: 16 bits*/
215#define ROBO_SECURE_DST_PORT_MASK 0x32 /* Secure Dest Port Mask: 16 bits */
216
217
218/* BCM5325m ARL IO REGISTERS (0x05) REGISTER MAP: 8/16/48/64 bit regs */
219#define ARL_TABLE_WRITE 0 /* for read/write state in control reg */
220#define ARL_TABLE_READ 1 /* for read/write state in control reg */
221#ifdef BCM5380
222#define ARL_VID_BYTES 2 /* number of bytes for VID */
223#else
224#define ARL_VID_BYTES 1 /* number of bytes for VID */
225#endif
226typedef struct _ROBO_ARL_RW_CTRL_STRUC
227{
228 unsigned char ARLrw:1; /* ARL read/write (1=read) */
229 unsigned char rsvd:6; /* reserved */
230 unsigned char ARLStart:1; /* ARL start/done (1=start) */
231} ROBO_ARL_RW_CTRL_STRUC;
232typedef struct _ROBO_ARL_SEARCH_CTRL_STRUC
233{
234 unsigned char valid:1; /* ARL search result valid */
235 unsigned char rsvd:6; /* reserved */
236 unsigned char ARLStart:1; /* ARL start/done (1=start) */
237} ROBO_ARL_SEARCH_CTRL_STRUC;
238typedef struct _ROBO_ARL_ENTRY_CTRL_STRUC
239{
240 unsigned char portID:4; /* port id */
241 unsigned char chipID:2; /* chip id */
242 unsigned char rsvd:5; /* reserved */
243 unsigned char prio:2; /* priority */
244 unsigned char age:1; /* age */
245 unsigned char staticEn:1; /* static */
246 unsigned char valid:1; /* valid */
247} ROBO_ARL_ENTRY_CTRL_STRUC;
248typedef struct _ROBO_ARL_SEARCH_RESULT_CTRL_STRUC
249{
250 unsigned char portID:4; /* port id */
251 unsigned char rsvd:1; /* reserved */
252 unsigned char vid:8; /* vlan id */
253 unsigned char age:1; /* age */
254 unsigned char staticEn:1; /* static */
255 unsigned char valid:1; /* valid */
256} ROBO_ARL_SEARCH_RESULT_CTRL_STRUC;
257typedef struct _ROBO_ARL_ENTRY_MAC_STRUC
258{
259 unsigned char macBytes[6]; /* MAC address */
260} ROBO_ARL_ENTRY_MAC_STRUC;
261
262typedef struct _ROBO_ARL_ENTRY_STRUC
263{
264 ROBO_ARL_ENTRY_MAC_STRUC mac; /* MAC address */
265 ROBO_ARL_ENTRY_CTRL_STRUC ctrl; /* control bits */
266} ROBO_ARL_ENTRY_STRUC;
267
268typedef struct _ROBO_ARL_SEARCH_RESULT_STRUC
269{
270 ROBO_ARL_ENTRY_MAC_STRUC mac; /* MAC address */
271 ROBO_ARL_SEARCH_RESULT_CTRL_STRUC ctrl; /* control bits */
272} ROBO_ARL_SEARCH_RESULT_STRUC;
273
274/* multicast versions of ARL entry structs */
275typedef struct _ROBO_ARL_ENTRY_MCAST_CTRL_STRUC
276{
277 unsigned int portMask:12;/* multicast port mask */
278 unsigned char prio:1; /* priority */
279 unsigned char gigPort:1; /* gigabit port 1 mask */
280 unsigned char staticEn:1; /* static */
281 unsigned char valid:1; /* valid */
282} ROBO_ARL_ENTRY_MCAST_CTRL_STRUC;
283typedef struct _ROBO_ARL_SEARCH_RESULT_MCAST_CTRL_STRUC
284{
285 unsigned int portMask:13; /* multicast port mask */
286 unsigned char age:1; /* age */
287 unsigned char staticEn:1; /* static */
288 unsigned char valid:1; /* valid */
289} ROBO_ARL_SEARCH_RESULT_MCAST_CTRL_STRUC;
290/* BCM5350 extension register */
291typedef struct _ROBO_ARL_SEARCH_RESULT_EXTENSION
292{
293 unsigned int prio:2; /* priority */
294 unsigned int portMask:1; /* MSB (MII) of port mask for multicast */
295 unsigned int reserved:5;
296} ROBO_ARL_SEARCH_RESULT_EXTENSION;
297
298typedef struct _ROBO_ARL_ENTRY_MCAST_STRUC
299{
300 ROBO_ARL_ENTRY_MAC_STRUC mac; /* MAC address */
301 ROBO_ARL_ENTRY_MCAST_CTRL_STRUC ctrl; /* control bits */
302} ROBO_ARL_ENTRY_MCAST_STRUC;
303typedef struct _ROBO_ARL_SEARCH_RESULT_MCAST_STRUC
304{
305 ROBO_ARL_ENTRY_MAC_STRUC mac; /* MAC address */
306 ROBO_ARL_SEARCH_RESULT_MCAST_CTRL_STRUC ctrl; /* control bits */
307} ROBO_ARL_SEARCH_RESULT_MCAST_STRUC;
308
309#define ROBO_ARL_RW_CTRL 0x00 /* ARL Read/Write Control : 8bit */
310#define ROBO_ARL_MAC_ADDR_IDX 0x02 /* MAC Address Index: 48bit */
311#define ROBO_ARL_VID_TABLE_IDX 0x08 /* VID Table Address Index: 8bit */
312#define ROBO_ARL_ENTRY0 0x10 /* ARL Entry 0 : 64 bit */
313#define ROBO_ARL_ENTRY1 0x18 /* ARL Entry 1 : 64 bit */
314#define ROBO_ARL_SEARCH_CTRL 0x20 /* ARL Search Control: 8bit */
315#define ROBO_ARL_SEARCH_ADDR 0x22 /* ARL Search Address: 16bit */
316#define ROBO_ARL_SEARCH_RESULT 0x24 /* ARL Search Result: 64bit */
317#define ROBO_ARL_SEARCH_RESULT_EXT 0x2c /* ARL Search Result Extension (5350): 8bit */
318#define ROBO_ARL_VID_ENTRY0 0x30 /* ARL VID Entry 0: 64bit */
319#define ROBO_ARL_VID_ENTRY1 0x32 /* ARL VID Entry 1: 64bit */
320
321/* BCM5325m MANAGEMENT FRAME REGISTERS (0x6) REGISTER MAP: 8/16 bit regs */
322#define ROBO_MGMT_FRAME_RD_DATA 0x00 /* Management Frame Read Data :8bit*/
323#define ROBO_MGMT_FRAME_WR_DATA 0x01 /* Management Frame Write Data:8bit*/
324#define ROBO_MGMT_FRAME_WR_CTRL 0x02 /* Write Control: 16bit */
325#define ROBO_MGMT_FRAME_RD_STAT 0x04 /* Read Status: 16bit */
326
327/* BCM5325m MEMORY ACCESS REGISTERS (Page 0x08) REGISTER MAP: 32 bit regs */
328#define MEM_TABLE_READ 1 /* for read/write state in mem access reg */
329#define MEM_TABLE_WRITE 0 /* for read/write state in mem access reg */
330#define MEM_TABLE_ACCESS_START 1 /* for mem access read/write start */
331#define MEM_TABLE_ACCESS_DONE 0 /* for mem access read/write done */
332#define VLAN_TABLE_ADDR 0x3800 /* BCM5380 only */
333#ifdef BCM5380
334#define NUM_ARL_TABLE_ENTRIES 4096 /* number of entries in ARL table */
335#define NUM_VLAN_TABLE_ENTRIES 2048 /* number of entries in VLAN table */
336#define ARL_TABLE_ADDR 0 /* offset of ARL table start */
337#else
338#define NUM_ARL_TABLE_ENTRIES 2048 /* number of entries in ARL table */
339#define NUM_VLAN_TABLE_ENTRIES 256 /* number of entries in VLAN table */
340#define ARL_TABLE_ADDR 0x3800 /* offset of ARL table start */
341/* corresponding values for 5350 */
342#define NUM_ARL_TABLE_ENTRIES_5350 1024 /* number of entries in ARL table (5350) */
343#define NUM_VLAN_TABLE_ENTRIES_5350 16 /* number of entries in VLAN table */
344#define ARL_TABLE_ADDR_5350 0x1c00 /* offset of ARL table start (5350) */
345#endif
346typedef struct _ROBO_MEM_ACCESS_CTRL_STRUC
347{
348 unsigned int memAddr:14; /* 64-bit memory address */
349 unsigned char rsvd:4; /* reserved */
350 unsigned char readEn:1; /* read enable (0 == write) */
351 unsigned char startDone:1;/* memory access start/done */
352 unsigned int rsvd1:12; /* reserved */
353} ROBO_MEM_ACCESS_CTRL_STRUC;
354typedef struct _ROBO_MEM_ACCESS_DATA_STRUC
355{
356 unsigned int memData[2]; /* 64-bit data */
357 unsigned short rsvd; /* reserved */
358} ROBO_MEM_ACCESS_DATA_STRUC;
359
360#ifdef BCM5380
361typedef struct _ROBO_ARL_TABLE_DATA_STRUC
362{
363 unsigned char MACaddr[6]; /* MAC addr */
364 unsigned int portID:4; /* port ID */
365 unsigned int chipID:2; /* chip ID */
366 unsigned int rsvd:6; /* reserved */
367 unsigned int highPrio:1; /* high priority address */
368 unsigned int age:1; /* entry accessed/learned since ageing process */
369 unsigned int staticAddr:1;/* entry is static */
370 unsigned int valid:1; /* entry is valid */
371 unsigned int vid:12; /* vlan id */
372 unsigned int rsvd2:4; /* reserved */
373} ROBO_ARL_TABLE_DATA_STRUC;
374#else
375typedef struct _ROBO_ARL_TABLE_DATA_STRUC
376{
377 unsigned char MACaddr[6]; /* MAC addr */
378 unsigned int portID:4; /* port ID */
379 unsigned int chipID:2; /* chip ID */
380 unsigned int rsvd:7; /* reserved */
381 unsigned int age:1; /* entry accessed/learned since ageing process */
382 unsigned int staticAddr:1;/* entry is static */
383 unsigned int valid:1; /* entry is valid */
384} ROBO_ARL_TABLE_DATA_STRUC;
385#endif
386
387/* multicast format*/
388typedef struct _ROBO_ARL_TABLE_MCAST_DATA_STRUC
389{
390 unsigned char MACaddr[6]; /* MAC addr */
391 unsigned int portMask:12;/* multicast port mask */
392 unsigned char prio:1; /* priority */
393 unsigned char gigPort:1; /* gigabit port 1 mask */
394 unsigned char staticEn:1; /* static */
395 unsigned char valid:1; /* valid */
396 unsigned int vid:12; /* vlan id */
397 unsigned int rsvd2:4; /* reserved */
398} ROBO_ARL_TABLE_MCAST_DATA_STRUC;
399#define ROBO_MEM_ACCESS_CTRL 0x00 /* Memory Read/Write Control :32bit*/
400#define ROBO_MEM_ACCESS_DATA 0x04 /* Memory Read/Write Data:64bit*/
401
402/* BCM5325m SWITCH PORT (0x10-18) REGISTER MAP: 8/16 bit regs */
403typedef struct _ROBO_MII_CTRL_STRUC
404{
405 unsigned char rsvd:8; /* reserved */
406 unsigned char duplex:1; /* duplex mode */
407 unsigned char restartAN:1;/* restart auto-negotiation */
408 unsigned char rsvd1:1; /* reserved */
409 unsigned char powerDown:1;/* power down */
410 unsigned char ANenable:1; /* auto-negotiation enable */
411 unsigned char speed:1; /* forced speed selection */
412 unsigned char loopback:1; /* loopback */
413 unsigned char reset:1; /* reset */
414} ROBO_MII_CTRL_STRUC;
415typedef struct _ROBO_MII_AN_ADVERT_STRUC
416{
417 unsigned char selector:5; /* advertise selector field */
418 unsigned char T10BaseT:1; /* advertise 10BaseT */
419 unsigned char T10BaseTFull:1; /* advertise 10BaseT, full duplex */
420 unsigned char T100BaseX:1; /* advertise 100BaseX */
421 unsigned char T100BaseXFull:1;/* advertise 100BaseX full duplex */
422 unsigned char noT4:1; /* do not advertise T4 */
423 unsigned char pause:1; /* advertise pause for full duplex */
424 unsigned char rsvd:2; /* reserved */
425 unsigned char remoteFault:1; /* transmit remote fault */
426 unsigned char rsvd1:1; /* reserved */
427 unsigned char nextPage:1; /* nex page operation supported */
428} ROBO_MII_AN_ADVERT_STRUC;
429#define ROBO_MII_CTRL 0x00 /* Port MII Control */
430#define ROBO_MII_STAT 0x02 /* Port MII Status */
431/* Fields of link status register */
432#define ROBO_MII_STAT_JABBER (1<<1) /* Jabber detected */
433#define ROBO_MII_STAT_LINK (1<<2) /* Link status */
434
435#define ROBO_MII_PHYID_HI 0x04 /* Port PHY ID High */
436#define ROBO_MII_PHYID_LO 0x06 /* Port PHY ID Low */
437#define ROBO_MII_ANA_REG 0x08 /* MII Auto-Neg Advertisement */
438#define ROBO_MII_ANP_REG 0x0a /* MII Auto-Neg Partner Ability */
439#define ROBO_MII_AN_EXP_REG 0x0c /* MII Auto-Neg Expansion */
440#define ROBO_MII_AN_NP_REG 0x0e /* MII next page */
441#define ROBO_MII_ANP_NP_REG 0x10 /* MII Partner next page */
442#define ROBO_MII_100BX_AUX_CTRL 0x20 /* 100BASE-X Auxiliary Control */
443#define ROBO_MII_100BX_AUX_STAT 0x22 /* 100BASE-X Auxiliary Status */
444#define ROBO_MII_100BX_RCV_ERR_CTR 0x24 /* 100BASE-X Receive Error Ctr */
445#define ROBO_MII_100BX_RCV_FS_ERR 0x26 /* 100BASE-X Rcv False Sense Ctr */
446#define ROBO_MII_AUX_CTRL 0x30 /* Auxiliary Control/Status */
447/* Fields of Auxiliary control register */
448#define ROBO_MII_AUX_CTRL_FD (1<<0) /* Full duplex link detected*/
449#define ROBO_MII_AUX_CTRL_SP100 (1<<1) /* Speed 100 indication */
450#define ROBO_MII_AUX_STATUS 0x32 /* Aux Status Summary */
451#define ROBO_MII_CONN_STATUS 0x34 /* Aux Connection Status */
452#define ROBO_MII_AUX_MODE2 0x36 /* Aux Mode 2 */
453#define ROBO_MII_AUX_ERR_STATUS 0x38 /* Aux Error and General Status */
454#define ROBO_MII_AUX_MULTI_PHY 0x3c /* Aux Multiple PHY Register*/
455#define ROBO_MII_BROADCOM_TEST 0x3e /* Broadcom Test Register */
456
457
458/* BCM5325m PORT MIB REGISTERS (Pages 0x20-0x24,0x28) REGISTER MAP: 64/32 */
459/* Tranmit Statistics */
460#define ROBO_MIB_TX_OCTETS 0x00 /* 64b: TxOctets */
461#define ROBO_MIB_TX_DROP_PKTS 0x08 /* 32b: TxDropPkts */
462#define ROBO_MIB_TX_BC_PKTS 0x10 /* 32b: TxBroadcastPkts */
463#define ROBO_MIB_TX_MC_PKTS 0x14 /* 32b: TxMulticastPkts */
464#define ROBO_MIB_TX_UC_PKTS 0x18 /* 32b: TxUnicastPkts */
465#define ROBO_MIB_TX_COLLISIONS 0x1c /* 32b: TxCollisions */
466#define ROBO_MIB_TX_SINGLE_COLLISIONS 0x20 /* 32b: TxSingleCollision */
467#define ROBO_MIB_TX_MULTI_COLLISIONS 0x24 /* 32b: TxMultiCollision */
468#define ROBO_MIB_TX_DEFER_TX 0x28 /* 32b: TxDeferred Transmit */
469#define ROBO_MIB_TX_LATE_COLLISIONS 0x2c /* 32b: TxLateCollision */
470#define ROBO_MIB_EXCESS_COLLISIONS 0x30 /* 32b: TxExcessiveCollision*/
471#define ROBO_MIB_FRAME_IN_DISCARDS 0x34 /* 32b: TxFrameInDiscards */
472#define ROBO_MIB_TX_PAUSE_PKTS 0x38 /* 32b: TxPausePkts */
473
474/* Receive Statistics */
475#define ROBO_MIB_RX_OCTETS 0x44 /* 64b: RxOctets */
476#define ROBO_MIB_RX_UNDER_SIZE_PKTS 0x4c /* 32b: RxUndersizePkts(runts)*/
477#define ROBO_MIB_RX_PAUSE_PKTS 0x50 /* 32b: RxPausePkts */
478#define ROBO_MIB_RX_PKTS_64 0x54 /* 32b: RxPkts64Octets */
479#define ROBO_MIB_RX_PKTS_65_TO_127 0x58 /* 32b: RxPkts64to127Octets*/
480#define ROBO_MIB_RX_PKTS_128_TO_255 0x5c /* 32b: RxPkts128to255Octets*/
481#define ROBO_MIB_RX_PKTS_256_TO_511 0x60 /* 32b: RxPkts256to511Octets*/
482#define ROBO_MIB_RX_PKTS_512_TO_1023 0x64 /* 32b: RxPkts512to1023Octets*/
483#define ROBO_MIB_RX_PKTS_1024_TO_1522 0x68 /* 32b: RxPkts1024to1522Octets*/
484#define ROBO_MIB_RX_OVER_SIZE_PKTS 0x6c /* 32b: RxOversizePkts*/
485#define ROBO_MIB_RX_JABBERS 0x70 /* 32b: RxJabbers*/
486#define ROBO_MIB_RX_ALIGNMENT_ERRORS 0x74 /* 32b: RxAlignmentErrors*/
487#define ROBO_MIB_RX_FCS_ERRORS 0x78 /* 32b: RxFCSErrors */
488#define ROBO_MIB_RX_GOOD_OCTETS 0x7c /* 32b: RxGoodOctets */
489#define ROBO_MIB_RX_DROP_PKTS 0x84 /* 32b: RxDropPkts */
490#define ROBO_MIB_RX_UC_PKTS 0x88 /* 32b: RxUnicastPkts */
491#define ROBO_MIB_RX_MC_PKTS 0x8c /* 32b: RxMulticastPkts */
492#define ROBO_MIB_RX_BC_PKTS 0x90 /* 32b: RxBroadcastPkts */
493#define ROBO_MIB_RX_SA_CHANGES 0x94 /* 32b: RxSAChanges */
494#define ROBO_MIB_RX_FRAGMENTS 0x98 /* 32b: RxFragments */
495#define ROBO_MIB_RX_EXCESS_SZ_DISC 0x9c /* 32b: RxExcessSizeDisc*/
496#define ROBO_MIB_RX_SYMBOL_ERROR 0xa0 /* 32b: RxSymbolError */
497
498/* BCM5350 MIB Statistics */
499/* Group 0 */
500#define ROBO_MIB_TX_GOOD_PKTS 0x00 /* 16b: TxGoodPkts */
501#define ROBO_MIB_TX_UNICAST_PKTS 0x02 /* 16b: TxUnicastPkts */
502#define ROBO_MIB_RX_GOOD_PKTS 0x04 /* 16b: RxGoodPkts */
503#define ROBO_MIB_RX_GOOD_UNICAST_PKTS 0x06 /* 16b: RxGoodUnicastPkts */
504/* Group 1 */
505#define ROBO_MIB_TX_COLLISION 0x00 /* 16b: TxCollision */
506#define ROBO_MIB_TX_OCTETS_5350 0x02 /* 16b: TxOctets */
507#define ROBO_MIB_RX_FCS_ERRORS_5350 0x04 /* 16b: RxFCSErrors */
508#define ROBO_MIB_RX_GOOD_OCTETS_5350 0x06 /* 16b: RxGoodOctets */
509
510/* BCM5325m QoS REGISTERS (Page 0x30) REGISTER MAP: 8/16 */
511#define ROBO_QOS_CTRL 0x00 /* 16b: QoS Control Register */
512#define ROBO_QOS_LOCAL_WEIGHT_CTRL 0x10 /* 8b: Local HQ/LQ Weight Register*/
513#define ROBO_QOS_CPU_WEIGHT_CTRL 0x12 /* 8b: CPU HQ/LQ Weight Register*/
514#define ROBO_QOS_PAUSE_ENA 0x13 /* 16b: Qos Pause Enable Register*/
515#define ROBO_QOS_PRIO_THRESHOLD 0x15 /* 8b: Priority Threshold Register*/
516#define ROBO_QOS_RESERVED 0x16 /* 8b: Qos Reserved Register */
517
518/* BCM5325m VLAN REGISTERS (Page 0x34) REGISTER MAP: 8/16bit */
519typedef struct _ROBO_VLAN_CTRL0_STRUC
520{
521 unsigned char frameControlP:2; /* 802.1P frame control */
522 unsigned char frameControlQ:2; /* 802.1Q frame control */
523 unsigned char dropMissedVID:1; /* enable drop missed VID packet */
524 unsigned char vidMacHash:1; /* VID_MAC hash enable */
525 unsigned char vidMacCheck:1; /* VID_MAC check enable */
526 unsigned char VLANen:1; /* 802.1Q VLAN enable */
527} ROBO_VLAN_CTRL0_STRUC;
528#define VLAN_TABLE_WRITE 1 /* for read/write state in table access reg */
529#define VLAN_TABLE_READ 0 /* for read/write state in table access reg */
530#define VLAN_ID_HIGH_BITS 0 /* static high bits in table access reg */
531#define VLAN_ID_MAX 255 /* max VLAN id */
532#define VLAN_ID_MAX5350 15 /* max VLAN id (5350) */
533#define VLAN_ID_MASK VLAN_ID_MAX /* VLAN id mask */
534#ifdef BCM5380
535#define VLAN_UNTAG_SHIFT 13 /* for postioning untag bits in write reg */
536#define VLAN_VALID 0x4000000 /* valid bit in write reg */
537#else
538#define VLAN_UNTAG_SHIFT 7 /* for postioning untag bits in write reg */
539#define VLAN_VALID 0x4000 /* valid bit in write reg */
540/* corresponding values for 5350 */
541#define VLAN_UNTAG_SHIFT_5350 6 /* for postioning untag bits in write reg */
542#define VLAN_VALID_5350 0x00100000 /* valid bit in write reg */
543#endif
544typedef struct _ROBO_VLAN_TABLE_ACCESS_STRUC
545{
546 unsigned char VLANid:8; /* VLAN ID (low 8 bits) */
547 unsigned char VLANidHi:4; /* VLAN ID (fixed upper portion) */
548 unsigned char readWriteState:1; /* read/write state (write = 1) */
549 volatile unsigned char readWriteEnable:1; /* table read/write enable */
550 unsigned char rsvd:2; /* reserved */
551} ROBO_VLAN_TABLE_ACCESS_STRUC;
552#ifdef BCM5380
553typedef struct _ROBO_VLAN_READ_WRITE_STRUC
554{
555 unsigned int VLANgroup:13;/* VLAN group mask */
556 unsigned int VLANuntag:13;/* VLAN untag enable mask */
557 unsigned char valid:1; /* valid */
558 unsigned char rsvd:5; /* reserved */
559} ROBO_VLAN_READ_WRITE_STRUC;
560#else
561typedef struct _ROBO_VLAN_READ_WRITE_STRUC
562{
563 unsigned char VLANgroup:7; /* VLAN group mask */
564 unsigned char VLANuntag:7; /* VLAN untag enable mask */
565 unsigned char valid:1; /* valid */
566 unsigned char rsvd:1; /* reserved */
567} ROBO_VLAN_READ_WRITE_STRUC;
568typedef struct _ROBO_VLAN_READ_WRITE_STRUC_5350
569{
570 unsigned char VLANgroup:6; /* VLAN group mask */
571 unsigned char VLANuntag:6; /* VLAN untag enable mask */
572 unsigned char highVID:8; /* upper bits of vid */
573 unsigned char valid:1; /* valid */
574 unsigned int rsvd:11; /* reserved */
575} ROBO_VLAN_READ_WRITE_STRUC_5350;
576#endif
577#define ROBO_VLAN_CTRL0 0x00 /* 8b: VLAN Control 0 Register */
578#define ROBO_VLAN_CTRL1 0x01 /* 8b: VLAN Control 1 Register */
579#define ROBO_VLAN_CTRL2 0x02 /* 8b: VLAN Control 2 Register */
580#define ROBO_VLAN_CTRL3 0x03 /* 8b: VLAN Control 3 Register */
581#define ROBO_VLAN_CTRL4 0x04 /* 8b: VLAN Control 4 Register */
582#define ROBO_VLAN_CTRL5 0x05 /* 8b: VLAN Control 5 Register */
583#define ROBO_VLAN_TABLE_ACCESS 0x08 /* 14b: VLAN Table Access Register */
584#define ROBO_VLAN_TABLE_ACCESS_5350 0x06 /* 14b: VLAN Table Access Register (5350) */
585#define ROBO_VLAN_WRITE 0x0a /* 15b: VLAN Write Register */
586#define ROBO_VLAN_WRITE_5350 0x08 /* 15b: VLAN Write Register (5350) */
587#define ROBO_VLAN_READ 0x0c /* 15b: VLAN Read Register */
588#define ROBO_VLAN_PORT0_DEF_TAG 0x10 /* 16b: VLAN Port 0 Default Tag Register */
589#define ROBO_VLAN_PORT1_DEF_TAG 0x12 /* 16b: VLAN Port 1 Default Tag Register */
590#define ROBO_VLAN_PORT2_DEF_TAG 0x14 /* 16b: VLAN Port 2 Default Tag Register */
591#define ROBO_VLAN_PORT3_DEF_TAG 0x16 /* 16b: VLAN Port 3 Default Tag Register */
592#define ROBO_VLAN_PORT4_DEF_TAG 0x18 /* 16b: VLAN Port 4 Default Tag Register */
593#define ROBO_VLAN_PORTMII_DEF_TAG 0x1a /* 16b: VLAN Port MII Default Tag Register */
594/* 5380 only */
595#define ROBO_VLAN_PORT5_DEF_TAG 0x1a /* 16b: VLAN Port 5 Default Tag Register */
596#define ROBO_VLAN_PORT6_DEF_TAG 0x1c /* 16b: VLAN Port 6 Default Tag Register */
597#define ROBO_VLAN_PORT7_DEF_TAG 0x1e /* 16b: VLAN Port 7 Default Tag Register */
598
599/* obsolete */
600#define ROBO_VLAN_PORT0_CTRL 0x00 /* 16b: Port 0 VLAN Register */
601#define ROBO_VLAN_PORT1_CTRL 0x02 /* 16b: Port 1 VLAN Register */
602#define ROBO_VLAN_PORT2_CTRL 0x04 /* 16b: Port 2 VLAN Register */
603#define ROBO_VLAN_PORT3_CTRL 0x06 /* 16b: Port 3 VLAN Register */
604#define ROBO_VLAN_PORT4_CTRL 0x08 /* 16b: Port 4 VLAN Register */
605#define ROBO_VLAN_IM_PORT_CTRL 0x10 /* 16b: Inverse MII Port VLAN Reg */
606#define ROBO_VLAN_SMP_PORT_CTRL 0x12 /* 16b: Serial Port VLAN Register */
607#define ROBO_VLAN_PORTSPI_DEF_TAG 0x1c /* 16b: VLAN Port SPI Default Tag Register */
608#define ROBO_VLAN_PRIORITY_REMAP 0x20 /* 24b: VLAN Priority Re-Map Register */
609
610#ifndef _CFE_
611#pragma pack()
612#endif
613
614
615#endif /* !__BCM535M_H_ */
616
617
618
619
620
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